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Complementary FET로 열어가는 반도체 미래 기술

2023-12-01 org.kosen.entty.User@2e6e5ed9 운영자(kosenadmin)

분야

전기/전자

발행기관

한국전자통신연구원

발행일

2023-12-01

URL

https://ettrends.etri.re.kr/ettrends/205/0905205006/

첨부파일

With semiconductor scaling approaching the physical limits, devices including CMOS (complementary metal-oxide-semiconductor) components have managed to overcome yet are currently struggling with several technical issues like short-channel effects. Evolving from the process node of 22 nm with FinFET (fin field effect transistor), state-of-the-art semiconductor technology has reached the 3 nm node with the GAA-FET (gate-all-around FET), which appropriately addresses the main issues of power, performance, and cost. Technical problems remain regarding the foundry of GAA-FET, and next-generation devices called post-GAA transistors have not yet been devised, except for the CFET (complementary FET). We introduce a CFET that spatially stacks p- and n-channel FETs on the same footprint and describe its structure and fabrication. Technical details like stacking of nanosheets, special spacers, hetero-epitaxy, and selective recess are more thoroughly reviewed than in similar articles on CFET fabrication.

Ⅰ. 트랜지스터 스케일링
Ⅱ. Complementary FET(CFET)
Ⅲ. Back Side Power Delivery Network(BSPDN) 기술
Ⅳ. 결론
용어해설
약어 정리

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