KOSEN 한인과학기술자네트워크

>안녕하세요.>현재 연구/개발이 진행되고 있는 UAV (unmanned air vehicle) or MAV(micro air vehicle)에서 scale (대중소 크기)에 따라 주로 사용되는 CPU (microcontroller and/or processor), IDE(개발환경), OS(operating system), technical spec. 등 이 어떻게 다른지 궁금하네요. >대부분의 내용들이 기사거리로만 취급하고 있어서 실제로 관심있는 1 m^3 급 이하의 tech. spec. 들은 찾기가 어렵네요. 단편적인 자료라도 아시는 대로 부탁드립니다. >체계적으로 분류된 자료나 웹사이트 정보 주시면 더욱 감사하겠습니다. 역시 그렇고 그렇군요. 거의 독점에 가까운 cpu, ide, os 를 사용하고들 있네요. 관심있으신 분들 참고하세요. Key features Like the original Nios, the Nios II architecture is a RISC soft-core architecture which is implemented entirely in the programmable logic and memory blocks of Altera FPGAs. The soft-core nature of the Nios II processor lets the system designer specify and generate a custom Nios II core, tailored for his or her specific application requirements. System designers can extend the Nios II's basic functionality by adding a predefined memory management unit, or defining custom instructions and custom peripherals. [edit] Custom instructions Similar to native Nios II instructions, user-defined instructions accept values from up to two 32-bit source registers and optionally write back a result to a 32-bit destination register. By using custom instructions, the system designers can fine-tune the system hardware to meet performance goals and also the designer can easily handle the instruction as a macro in C/C++. [edit] Custom peripherals For performance-critical systems that spend most CPU cycles executing a specific section of code, a user-defined peripheral can potentially offload part or all of the execution of a software-algorithm to user-defined hardware logic, improving power-efficiency or application throughput. [edit] Memory Management Unit Introduced with Quartus 8.0, the optional MMU enables Nios II to run operating systems which require hardware-based paging and protection, such as the Linux kernel. Without an MMU, Nios is restricted to operating systems which use a simplified protection and virtual memory-model: e.g., ？Clinux and FreeRTOS. [edit] Memory Protection Unit Introduced with Quartus 8.0, the optional MPU provides memory protection similar to that provided by an MMU but with a simpler programming model and without the performance overhead associated with an MMU. [edit] Nios II CPU family Nios II is offered in 3 different configurations: Nios II/f (fast), Nios II/s (standard), and Nios II/e (economy). [edit] Nios II/f The Nios II/f core is designed for maximum performance at the expense of core size. Features of Nios II/f include: Separate instruction and data caches (512 B to 64 kB) Optional MMU or MPU Access to up to 2 GB of external address space Optional tightly coupled memory for instructions and data Six-stage pipeline to achieve maximum DMIPS/MHz Single-cycle hardware multiply and barrel shifter Optional hardware divide option Dynamic branch prediction Up to 256 custom instructions and unlimited hardware accelerators JTAG debug module Optional JTAG debug module enhancements, including hardware breakpoints, data triggers, and real-time trace [edit] Nios II/s Nios II/s core is designed to maintain a balance between performance and cost. Features of Nios II/s include: Instruction cache Up to 2 GB of external address space Optional tightly coupled memory for instructions 6-stage pipeline Static branch prediction Hardware multiply, divide, and shift options Up to 256 custom instructions JTAG debug module Optional JTAG debug module enhancements, including hardware breakpoints, data triggers, and real-time trace [edit] Nios II/e The Nios II/e core is designed for smallest possible logic utilization of FPGAs. This is especially efficient for low-cost Cyclone II FPGA applications. Features of Nios II/e include: Up to 2 GB of external address space JTAG debug module Complete systems in fewer than 700 LEs Optional debug enhancements Up to 256 custom instructions