The relentless scaling of feature sizes exemplified by Moore’s Law has enabled the application of sophisticated signal processing techniques to high speed broadband communication links employing mixed analog and digital architectures and circuits. The Nanoscale Advanced Integrated Systems (NAIS) Laboratory focuses on developing innovative solutions by jointly optimizing algorithm, architecture, and circuits for broadband systems.
Recent IC developments include low power 100Gb/s Ethernet transceiver ICs. Adaptive digital phase rotator based clock and data recovery (CDR) scheme was developed to tolerate various interferences including thermal noise and substrate injections prevalent in high speed mixed mode system ICs. In addition, the designed CDR maintains low clock jitter while providing sufficient input jitter tolerance through adaptive bandwidth control.