KOSEN 한인과학기술자네트워크

• Analog-to-Digital Converters (ADCs)
• Precision Analog Circuits
• Smart Sensor Design in CMOS Technology
• CMOS Image Sensors

A 0.53pJK2 7000μm2 resistor-based temperature sensor with an inaccuracy of ±0.35°C (3σ) in 65nm CMOS

IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2018.

Compact R-based temperature sensor for dense thermal monitoring

This paper presents a highly digital resistor-based temperature sensor in 65nm CMOS, which achieves a  3σ  inaccuracy of  ±0.36？C  from −40 to 85°C and 2.8mK resolution at a 1kS/s sampling rate. The sensor can operate from 0.85V supplies, while consuming only  68μW . This corresponds to a resolution FOM of 0.53pJ.K2, which is more than  15×  less than a previous WB-based FLL sensor. Furthermore, the sensor occupies only  7000μm2 , which is  13×  less than previous works and comparable to state-of-the-art BJT-, MOS-, and TD-based sensors. These advances are achieved by the use of an RC polyphase filter as a sensing element, which is then read out by a highly digital frequency-locked loop.

A 6.9mW 120fps 28×50 Capacitive Touch Sensor with 41.7dB SNR for 1mm Stylus Using Current-Driven ΔΣ ADCs

IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2017.

The Most Efficient Capacitive Touch IC

This paper presents a 120fps 28×50 touch sensor that achieves 41.7dB SNR for 1mm-φ stylus, while consuming 6.9mW, which results in an energy efficiency of 0.41nJ/step, for a 4× improvement compared to state-of-the-art stylus touch sensors. This is achieved by a current-driven ΔΣ ADC architecture, which implements charge balancing between a reference charge and a differential current from adjacent channels, directly interfacing with 2nd-order ΔΣ modulators. In contrast to previous works, the current-driven ΔΣ ADC only needs to digitize small differential currents, which relaxes requirements of the frontend amplifier, resulting in a large power reduction.

IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2017.

The first CPHY Transceiver

Single-ended signaling has been used for LPDDR interfaces due to 100% pin efficiency. However, as the data rate increases simultaneous switching noise (SSN) limits the bandwidth. To address this issue, differential coding schemes that encode signals over multiple channels have been explored to achieve pin efficiency and SSN robustness. This paper presents a 1V 15.6Gb/s C-PHY transceiver using tri-level signaling that consumes only 7.8mW, resulting in an energy-efficiency of 0.5pJ/b. Such a high efficiency is achieved by the use of a tri-level signaling, which is from C-PHY encoding scheme of MIPI alliance standards, in combination with an active-ground tri-level transmitter and a crosstalk-cancelled low-power receiver. 

IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2014.

All CMOS Temp. Sensor with ±0.4°C (3σ) Inaccuracy (1 point trim)

This work describes an all-CMOS temperature sensor intended for RFID applications that achieves both sub-1V operation and high accuracy (±0.4°C) over a wide temperature range (-40 to 125°C). It is also an ultra-low-power design: drawing 700nA from a 0.85V supply. This is achieved by the use of dynamic threshold MOSTs (DTMOSTs) as temperature-sensing devices, which are then read out by an inverter-based 2nd-order zoom ADC. Circuit errors are mitigated by the use of dynamic error-correction techniques, while DTMOST spread is reduced by a single room temperature (RT) trim. The latter feature constitutes a significant advance over previous all-CMOS designs, which require two-point trimming to approach the same level of accuracy.

A 6.3µW 20bit Incremental Zoom-ADC with 6ppm INL and 1µV Offset

IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2013.

The World First ADC over 180dB FoM

A 20b Incremental analog-to-digital converter has been realized in a 0.16μm CMOS process. It employs a zoom ADC architecture, a novel inverter-based integrator and various dynamic error correction techniques to achieve 6ppm INL and 1μV offset, while dissipating only 6.3μW. It achieves a Schreier's FOM of 182.7dB, which represents a 16dB improvement on the state-of-the-art ADCs with similar performance. 

A CMOS Temperature Sensor with a Voltage Calibrated Inaccuracy of ±0.15°C (3σ) from -55 to 125°C

IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2012.

The most Energy-Efficient Precision CMOS Temperature Sensor

This work describes an energy-efficient CMOS temperature sensor intended for use in RFID tags. The sensor achieves an inaccuracy of ±0.15°C (3σ) over the military temperature range (-55 to 125°C) and dissipates only 27nJ/conversion: over 20× less than a previous sensor with comparable accuracy and resolution. This energy efficiency is achieved by the use of an improved charge-balancing scheme and a zoom ADC that combines a 5b coarse SAR conversion with a 10b fine 2nd-order ΔΣ conversion.

A 0.7 e^-_rms Temporal Readout Noise CMOS Image Sensor for Low Light Level Imaging

IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2012. 

Very Low Noise CMOS Imager 

For low-light-level imaging, the performance of a CMOS image sensor is usually limited by the temporal readout noise (TRN) generated from its analog readout circuit chain. Although a sub-electron TRN level can be achieved with a high-gain pixel-level amplifier, the pixel uniformity is highly impaired up to a few percent by its open-loop amplifier structure. The TRN can be suppressed without this penalty by employing either a high-gain column-level amplifier or a correlated multiple sampling (CMS) technique. However, only 1-to-2 electron TRN level has been reported with the individual use of these approaches, and the low-frequency noise of the in-pixel source follower i.e. 1/f and RTS noise is a further limitation. Therefore, by implementing a high-gain column-level amplifier and CMS technique together with an in-pixel buried-channel source follower, the TRN level can be reduced even further to the level of 0.7 e^-_rms.

IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2010. 

The World first CMOS Imager with fully implemented column-parallel ΔΣ ADCs 

This work presents a 2.1Mpixel, 120 frame/s CMOS image sensor with column-parallel delta-sigma (ΔΣ) ADC architecture. The use of a second-order ΔΣ ADC improves the conversion speed while reducing the random noise (RN) level as well. The ΔΣ ADC employing an inverter-based ΔΣ modulator and a compact decimation filter is accommodated within a fine pixel pitch of 2.25-μm and improves energy efficiency while providing a high frame-rate of 120 frame/s. A prototype image sensor has been fabricated with a 0.13-μm CMOS process. Measurement results show a RN of 2.4 e^-_rms and a dynamic range of 73 dB. The power consumption of the prototype image sensor is only 180 mW. This work achieves the energy efficiency of 1.7 e^- nJ, which is 3.5x less than the state-of-the art works. 

A 0.7V 36μW 85dB-DR Audio ΔΣ Modulator Using Class-C Inverter

IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2008. 

The World First ΔΣ ADC under 100fJ/Step ADC FoM

In this work, an ultra low-power switched-capacitor audio delta-sigma modulator is realized in a standard 0.18-μm CMOS process, exploiting the possibility of substitution of OTA with class-C inverter. The measurement results from the fabricated chip demonstrate 81-dB SNDR, 84-dB SNR and 85-dB DR for 20-kHz signal bandwidth. The power consumption is only 36 μW with a 0.7-V supply voltage. This work achieved 98-fJ/Step ADC FoM.