Research Area
- Neural Network Compression (active)
- Neural Network Processing Units (NPU) (active)
- Clock and Power Gating (active)
- High-level, Logic Synthesis, and Physical Design (active)
- 3D IC Design
- 3D physical design
- 3D clock path synthesis
- 3D power network delivery
- Flip-chip router, 3D timing analysis
- 3D thermal analysis and management
- Embedded Systems
- Compilation techniques: Leakage power aware instruction generation
- Software platform design for multimedia/wireless applications
- Simulation and GUI environment tool for reconfigurable processor
- Code generation technique for leakage cache power minimization
- Multi-banks code access optimization
- DRAM memory access code optimization
- Address code generation for DSP-oriented processors
- Low-energy variable partitioning/scheduling for embedded processor with multiple banks
- Low-energy task/voltage scheduling (OS) for real-time embedded systems
- Data arrangements in DRAMs for access optimization
- Cache activity optimization for hard real-time embedded systems
- Low-power resource constrained bus encoding
- Voltage scheduling and allocation
- Access code optimization for embedded systems with multiple banks
- Low-energy code compression
- Thermal-Aware Design
- Thermal simulator tool
- Thermal-aware floorplanning
- Thermal-aware architecture/logic synthesis
- Logic synthesis for leakage current minimization
- Voltage island
- Architecture-Level Synthesis for System-on-Chip design
- Leakage-aware bus encode
- Interconnect/coupling-aware synthesis
- Unified (fabric-driven) synthesis and placement
- ALU design and arithmetic optimization
- Synthesis for low-power design architecture
- Leakage power optimization
- Logic-Level Synthesis
- Variation-aware false path analysis
- Synthesis/analysis for low-power logic circuit
- System (interface) synthesis
- High-Level Synthesis
- High-level synthesis for 3D IC design
- Synthesis for low power
- Memory synthesis
- Scheduling/allocation/testability for timing/area
- PhD Thesis
- Scheduling and Allocation Problems in High-level Synthesis (advisor: C. L. Liu, Univ. of Illinois at U-C)