- Main memory such as dynamic random access memory (DRAM) dissipates a significant portion of the total energy consumption and often becomes a major performance bottleneck of a system. Our lab works to resolve this problems by designing internal memory architecture, 3D-stacked memory, and processing-in-memory.
- - Design Accelerator for Neural Networks
Conventional structures of accelerators are inefficient for accelerating neural network on edge devices in terms of power consumption and chip area. Therefore it is important to design a small and power efficient logic to accelerate neural networks. -
- - Bayesian Neural Networks and Predictive Uncertainty Estimation
Predictive uncertainty estimation has been improved reliability and ability of generalization of Deep Neural Networks (DNNs). While non-Bayesian DNNs could be overfitted, compromised by adversarial attacks, or could not distinguish unseen inputs or inputs from out-of-distribution, Bayesian Neural Networks could because of their probabilistic nature of predicting uncertainty of their outputs. However, the probabilistic nature could slow not only training speed but inference speed of Bayesian NNs, which should be resolved for deploying Bayesian NNs to the real-world applications. Hence, we are interested in all aspects of Bayesian NNs and predictive uncertainty estimation including, but not limited to, HW/SW optimization of Bayesian neural models, applications using predictive uncertainty and data augmentation and generation for inducing uncertain answers from Bayesian NNs. -
- - Object Detection
Object detection from static image has been progressed by using convolutional neural networks. However, object detection in video is an challenging problem because of several situations in video such as camera defocus, object deformation, motion blur, etc. Moreover, detecting and tracking for all video frames also requires high computation. To resolve this problem, we researches deep-learning based efficient and accurate video object detector model and implementation.
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- LDPC codes over GF(q) with q > 2 (NB-LDPC) offer powerful error correction capability when the code length is short. Despite the excellent communication performance, NB-LDPC is not suitable for practical application because of the heavy decoding complexity. Our lab. have been researching on low complexity decoding schemes, decoding algorithms, HW implementation of the decoders.
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- Heterogenous computing uses several different types of chip simultaneously, such as CPU, GPU, DSP, NPU, and FPGA. Since each device has different characteristics, it is important to transfer a job to an appropriate device. We are studying how to analyze each device, and what is optimal mapping scheme for a given system.
