KOSEN 한인과학기술자네트워크

Smart Storage Systems

• Data movement cost from storage devices to compute nodes is extremely high for modern data processing applications. Such big data applications pay a significant fraction of their execution time on the data input/output (I/O) time. Near data processing (NDP) is a prominent approach by offloading part of computation to embedded storage processors. NDP is becoming a more viable option with SSDs, which equip embedded processors and page buffer memory. This computation potential in the embedded storage processors can facilitate active storage systems, which enable computing near storage or application-specific storage data management.
• “Graph Semantic Aware SSD” (ISCA ’19)
• “Summarizer” (MICRO ’17)

GPU Memory Hierarchy Architecture

• GPU’s memory operation is a critical performance bottleneck since lots of memory requests are issued from dozens of warps (or wavefronts) within a short time window. Thus, limited resources in memory subsystem suffer from low efficiency due to severe data contention and heavy data traffic. I characterized diverged memory requests in GPGPU applications to reveal main performance bottlenecks from the critical load instructions. I also investigated GPU’s unique data access patterns by global loads. Based on these observations I presented the GPU cache management method to utilize the data cache more efficiently.
• “Victimc Cache using Idle Register File” (ISCA ’19)
• “Access Pattern-Aware Cache Management” (ISCA ’17)
• “Revealing Critical Loads” (IISWC ’15)
• “Warped-Compression” (ISCA ’15)

Prefetch

• Long latency of memory operation is one of critical performance hurdles in general computing processors including GPUs. Prefetch can be one of prominent approach to hide this long latency of data fetch. I proposed an efficient GPU prefetch mechanism based on GPU’s unique software execution model and array index calculation approaches. I also suggested a warp scheduling scheme that can enhance the timeliness of the prefetcher.
• “CTA-Aware Prefetching and Scheduling” (IPDPS ’18)
• “Warped-Preexecution” (HPCA ’16)

Energy Efficient Computing

• Battery efficiency varies with usage patterns of mobile computing due to the non-ideal characteristics in converting chemical to electrical energy. Besides the efficiency of power delivery network decides actual lifetime of batteries. I measured end-point power usage patterns and battery discharge time by mobile applications. I presented the control method applying DVFS to CPUs, GPUs, and peripherals to maximize the efficiency of battery and power delivery network.