Research Interests
Neural Network-Friendly Hardware / Hardware-Friendly Neural Network
Network Compression: Pruning, Quantization
Efficient Sparse Matrix Handling in NN Hardware
Variable-Precision Neural Network Hardware
Multi-bit Neural Network with Bitwise Activation
Near-/In-Memory Neural Network Computing
Resistive Memory Based Neural Network Hardware
SRAM based Binary Neural Network Hardware
Mapping Large Neural Network on Memory Arrays
Minimizing the Overhead of Peripheral Circuits(ADC/DAC) for In-Memory DNN Computing
Process-Variation tolerant In-Memory NN Computing
Near-Memory NN Processing in 3D High Bandwidth Memory (HBM)
Spin Device based Neural Network Hardware
Spiking Neural Network (SNN) Hardware
FireFly: Large Scale CMOS SNN Hardware
Efficient Synapse Memory Structure
6T SRAM Cell based Integrated Transposable Synapse Memory
Multi-Core SNN Chip Architecture
Supervised Learning in SNN
Convolution Mapping on SNN Hardware
Hardware Security IP
CMOS True Random Number Generator (TRNG)
CMOS Physically Unclonable Function (PUF)
Device/Circuit Design for Exploratory Technology
Split-Gate Ambipolar Device/Circuit
Negative Transconductance Heterojunction Transistor
Multi-level Metal Interconnection for Organic Device Technology
국가
대한민국
소속기관
포항공과대학교 (학교)
연락처
054-279-8858 http://dicelab.postech.ac.kr/
책임자
김재준 jaejoon@postech.ac.kr