We are focusing on system-on-chip (SoC) technologies for mobile intelligent systems with extreme performance and energy-efficiency, which include high-performance low-power AI processor, mobile GPU, embedded CPU, etc. The ever increasing demand for the computing power within limited power budgets and footprints of mobile devices opens up challenges for energy-efficient SoC designs. Therefore, lowering power and area overheads of the SoCs while increasing their performance becomes an essential technique for smart mobile devices and intelligent vehicles. From this perspective, our goal is to increase the power and area efficiency of the SoCs as well as to improve their performance by exploring innovations through the entire SoC design stack from algorithm, architecture, and circuit to design methodology. Such an integral approach requires cross-layer optimizations across the whole design stack. Hence, co-optimizations of embedded software, architecture, and circuits are to be mainly investigated in the MSSL.

Researches in MSSL include:

• Power-efficient mobile GPU

3D computer graphics requires high computing power while mobile devices provide only limited computing resources and battery lifetime. These contradictory constraints placed on mobile GPU design present challenges to developing power efficient mobile graphics processing devices. To cope with this problem, we are to explore algorithmic transforms of graphics pipeline, processor architectures for graphics stream processing, and arithmetic schemes to reduce computational complexities and thereby increasing the power-efficiency.

• High-performance embedded CPU

Recent embedded superscalar microprocessors such as ARM’s Cortex-A series incorporate a lot of high-performance architectural features such as speculative and out-of-order execution pipeline, multi-level cache system, and consistency models for the multi-core platforms. We are to investigate several high-performance architecture and high-speed circuit design techniques including dynamic circuits, high-speed flip-flops, and high-speed SRAMs to speed up these cores to multiple GHz.

• Low-power SoC design

As the integration level of SoC is getting higher, power dissipation is becoming the major limiting factor of SoC designs for wireless mobile devices. Therefore, sophisticated power management techniques such as power gating and body biasing to suppress static power as well as dynamic voltage and frequency scaling to control dynamic power are widely explored. From this perspective, we are to explore power management units and VLSI technologies together with operating system’s power scheduling algorithms exploiting a hardware and software co-optimization.

• Embedded software platform

Embedded systems should be optimized together with its system platform such as runtime system as well as operating system for a higher performance and energy-efficiency. So we plan to investigate the co-optimization of system software with the underlying hardware architecture taking account of the application domains. In addition, we are to further explore GPU related software platforms such as OpenCL to achieve more advanced profiles for the performance and power-efficiency.