Deep Neural Network Accelerator Design
- In-memory-computing for data-centric neural network accelerator
- Approximate computing techniques for low power consumption
- Zero-aware hardware architecture (zero weight from pruning-training, zero input from ReLU-inference)
- Various implementation techniques based on domain change
Digital Signal Processors
- Efficient interface design of embedded memory for low power image processing (MPEG/H.264) applications
- Memory based computation of cryptography processor and physical unclonable function (PUF)
Embedded Memory Design
- Emerging memory (STT-MRAM, SOT-MRAM, Domain-Wall Memory) design
- Memory (SRAM/eDRAM/CAM) customization in application-specific purpose
- Memory yield estimation modeling
국가
대한민국
소속기관
숙명여자대학교 (학교)
연락처
02-710-7731 https://sites.google.com/sookmyung.ac.kr/vlsisys
책임자
최웅 woongchoi@sookmyung.ac.kr